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BuildCircuit is an online store for selling electronics kits and components related to Arduino, Raspberry Pi, etc. We operate from Sydney, Australia.

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CD4017

AU $1.50
SKU:
BC-5622
Shipping:
Calculated at checkout
Current Stock:
20
Quantity:

This product is shipped from Sydney, Australia. Worldwide shipping available- we ship to USA, Canada, New Zealand, UK, EU and Non-EU countries.

The CD4017 is the one of the most popular Decade Counter (Divided by 10 Counter). It is a 5 Stage Divide by 10 Johnson Counter with 10 Decoded outputs. It has a wide supply voltage range from 3V to 15V and is compatible with TTL. It has a medium speed of operation, typically 5Mhz. Its applications includes industrial electronics, remote metering, automotive, medical electronics, instrumentation and alarm systems.

CD4017 Pin Diagram

CD4017 Pin Diagram

CD4017 Pin Diagram

The above diagram shows the pin out of CD4017B, Dual-In-line package.

Pin Functions

Vcc

 

It is the supply voltage terminal of the IC. Being a CMOS IC it has a wide supply voltage range from 3V to 15V.

 

Vss

 

It is the ground pin or common pin of the IC CD4017. It should be connected to the negative terminal of the DC Power supply or battery.

 

Q0 – Q9

 

These are the 10 decoded outputs of the CD 4017 IC. One of the 10 decoded outputs may be high at a time.

 

Clock

 

It is the clock pin of the counter. Q0 goes high during the rise of the first clock cycle. Q0 goes low and Q1 goes high during the rise of the second clock cycle, and so on..

 

Clock Enable

 

This is the active low enable pin for clock input. If this input is high the counter will not count clock cycles.

 

Carry Out

 

This pin is used to indicate that the count exceeds 10. This pin goes low when the output Q5 goes high and goes high when the output Q0 goes high.

 

Reset

 

This is the reset pin of the IC. When this pin goes high, the output pin Q0 will go high.

 

Timing Diagram – CD4017

 

CD4017 Timing Diagram

CD4017 Timing Diagram

 

Clock is applied to the terminal continuously. When RESET signal is applied the IC will reset and the output Q0 will become HIGH. During the positive transaction of next clock cycle Q0 goes LOW and Q1 goes HIGH, and so on.. The output Carry Out becomes LOW and HIGH when the output Q5 goes HIGH and Q1 goes HIGH respectively. Clock Enable input is an Active Low input pin, when it is high the counter will not count clock cycles.

 

Documents:

Experiments

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